Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Expert Solution & Answer
Chapter 6.6, Problem 6.21PP
Explanation of Solution
Estimating time in CPU cycles:
It is given that the sustained throughput using large strides from L1 is: 12,000 MB/s.
Clock frequency= 2,100 MHz
Individual read accesses= 8-byte long
Hence, one can estimate that it takes roughly
Expert Solution & Answer
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Problem 1.8 The following code segment, consisting of six instructions, needs to be
executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I)
xC(I) for 0 ≤ I ≤ 63.
Load R1, B(I)
/R1 - Memory (a + I)/
Load R2, C(I)
Multiply R1, R2
Load R3, A(I)
Add R3, R1
Store D(I), R3
t
/R2 Memory (8 + 1)/
/R1 - (R1) × (R2)/
/R3
-
Memory (7 + I)/
-
/R3 (R3) + (R1)/
/Memory (0 + I) ← (R3)/
where R1, R2, and R3 are CPU registers, (R1) is the content of R1, a, ß,7, and are
the starting memory addresses of arrays B(1), C(I), A(I), and D(I), respectively. Assume
four clock cycles for each Load or Store, two cycles for the Add, and eight cycles for the
Multiply on either a uniprocessor or a single PE in an SIMD machine.
(a) Calculate the total
ber of CPU cycles needed to execute the above code seg-
ment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring
all other time delays.
(b) Consider the use of an SIMD computer with 64 PEs to execute the above…
Problem
Question 03 (CO3) [0.5 + 0.5 = 1]: Given below are the contents of several Intel 8086 registers
and PHYSICAL memory addresses (ALL in hexadecimal):
Registers:
Memory Locations [Physical Address] = Contents
[05000] = 3300
[06000] = 4444
[07000] = 5555
[95000] = 367A
[96000] = 6666
[97000] = 10C5
DI = 3000
%3D
BX = 3000
%3D
ВР 3 С345
For the following instructions, determine the contents of AX after the each of the instruction has
been executed:
(а) MOV
(b) MOV
АХ, ВР
АХ, [ВХ+DI]
AX =
AX
Question 4:
a) Translate the following C code to MIPS assembly code. Use a minimum number of instructions.
Assume that the values of a, b, i, and jare in registers $80, $s 1, $t0, and $t1, respectively.
Also, assume that register $s2 holds the base address of array D.
for (i=0; i
Chapter 6 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 6.1 - Prob. 6.1PPCh. 6.1 - Prob. 6.2PPCh. 6.1 - Prob. 6.3PPCh. 6.1 - Prob. 6.4PPCh. 6.1 - Prob. 6.5PPCh. 6.1 - Prob. 6.6PPCh. 6.2 - Prob. 6.7PPCh. 6.2 - Prob. 6.8PPCh. 6.4 - Prob. 6.9PPCh. 6.4 - Prob. 6.10PP
Ch. 6.4 - Prob. 6.11PPCh. 6.4 - Prob. 6.12PPCh. 6.4 - Prob. 6.13PPCh. 6.4 - Prob. 6.14PPCh. 6.4 - Prob. 6.15PPCh. 6.4 - Prob. 6.16PPCh. 6.5 - Prob. 6.17PPCh. 6.5 - Prob. 6.18PPCh. 6.5 - Prob. 6.19PPCh. 6.5 - Prob. 6.20PPCh. 6.6 - Prob. 6.21PPCh. 6 - Prob. 6.22HWCh. 6 - Prob. 6.23HWCh. 6 - Suppose that a 2 MB file consisting of 512-byte...Ch. 6 - The following table gives the parameters for a...Ch. 6 - The following table gives the parameters for a...Ch. 6 - Prob. 6.27HWCh. 6 - This problem concerns the cache in Practice...Ch. 6 - Suppose we have a system with the following...Ch. 6 - Suppose we have a system with following...Ch. 6 - Suppose that a program using the cache in Problem...Ch. 6 - Repeat Problem 6.31 for memory address0x16E8 A....Ch. 6 - Prob. 6.33HWCh. 6 - Prob. 6.34HWCh. 6 - Prob. 6.35HWCh. 6 - Prob. 6.36HWCh. 6 - Prob. 6.37HWCh. 6 - Prob. 6.38HWCh. 6 - Prob. 6.39HWCh. 6 - Given the assumptions in Problem 6.38, determine...Ch. 6 - You are writing a new 3D game that you hope will...Ch. 6 - Prob. 6.42HWCh. 6 - Prob. 6.43HWCh. 6 - Prob. 6.45HWCh. 6 - Prob. 6.46HW
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- Problem 1.8 The following code segment, consisting of six instructions, needs to be executed 64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I) xC(I) for 0 ≤ I≤ 63. Load R1, B(I) /R1 - Memory (a + I)/ Load R2, C(I) Multiply R1, R2 Load R3, A(I) Add R3, R1 Store D(I), R3 t /R2 Memory (8 + 1)/ /R1 - (R1) × (R2)/ /R3 - Memory (7 + I)/ - /R3 (R3) + (R1)/ /Memory (0 + I) ← (R3)/ where R1, R2, and R3 are CPU registers, (R1) is the content of R1, a, ß,7, and are the starting memory addresses of arrays B(1), C(I), A(I), and D(I), respectively. Assume four clock cycles for each Load or Store, two cycles for the Add, and eight cycles for the Multiply on either a uniprocessor or a single PE in an SIMD machine. (a) Calculate the total ber of CPU cycles needed to execute the above code seg- ment repeatedly 64 times on an SISD uniprocessor computer sequentially, ignoring all other time delays. (b) Consider the use of an SIMD computer with 64 PEs to execute the above…arrow_forward(e) Instruction(s) to copy contents at one memory location to another: C[g] =A[i+j-3). Assume i, j,g values are in registers x5, x6, x7. Assume base address in memory of Array data structures 'A, B' (or address in memory of 'A[O]' and 'B[O]') are stored in Registers x28, 29• In RISCV, only load and store instructions access memory locations • These instructions must follow a 'format' to access memory • Assume a 32 bit machine in all problems unless asked to assume otherwisearrow_forward[1] ( Show your work. Show hoe you compute memory address by using the effective memory address computation. Assume the following values are stored at the indicated memory addresses and registers: Address Value 0x100 OxFF 0x104 OxAB 0x108 0x13 0x10c 0x11 Register %rax %rcx %rdx $0x108 (%rax) 4(%rax) 9(%rax, %rdx) 260(%rcx,%rdx) OxFC (,%rcx, 4) (%rax, %rdx, 4) Value 0x100 0x1 0x3 Fill in the following table showing the values for the indicated operands: Operand Value %rax 0x104arrow_forward
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