A sequential circuit with two D flip-flops A and B, two inputs X and Y, and one output Z is specified by the following input equations: DA = XA + XY, DB = XB + XA, Z = XB (a) Draw the logic diagram of the circuit. (b) Derive the state table. (c) Derive the state diagram. (d) Is this a Mealy or a Moore machine?
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- 4-6. A sequential circuit with two D flip-flops A and B and input X and output Yis specified by the following input equations: Y = A + B D = X + B D = XA (a) Draw the logic diagram of the circuit. (b) Derive the state table. (c) Derive the state diagram. (d) Is this a Mealy or a Moore machine?Review Questions Question [4] For the given sequential circuit: a. What type of state machine is this circuit and why? b. Determine the flip-flop input equations and the output equations from the circuit. c. Derive the next-state equation for each flip-flop from its input equations. d. Derive the State table. e. Derive the State Graph. Determine the state sequence and output sequence if the initial state is So and the input sequence is X= 01100 B B KA CK JA KB CK to Clock Clock X" X- X' A B'Design a logic circuit with four inputs and one output that will produce "l" in the output only if the input patterns have odd number of zeros. a) Write the Boolean equation for the circuit in the simplest SOP form. b) Draw the logic circuit for the above equation in its simplest form. c) Re Design the logic circuit using NANI) gates only?
- H.W :- 1) A four logic-signal A,B,C,D are being used to represent a 4-bit binary number with A as the LSB and D as the MSB. The binary inputs are fed to a logic circuit that produces a logic 1 (HIGH) output only when the binary number is greater than 01102-610. Design this circuit. 2) repeat problem 1 for the output will be 0 (LOW) when the binary input is less than 01112-710- Saleem Lateef1. The synchronous finite state machine (FSM) with input X and output Z consisted of two D-flip-flops with positive edge triggering and asynchronous clear (Figure 1). The flip-flop input excitation and output forming logic were implemented with 2-to-1 multiplexers (note that in the multiplexer symbols data inputs DO are shown above inputs D1). Obtain the following: a) Excitation equations for flip-flop inputs (Q1*, Q0*) and the equation for output Z. b) Output type (Moore/Mealy). c) State table: next states (Q1*, Q0*) as functions of present states (Q1, QO) and X, show output Z values. d) State diagram: show output Z values. e) Output Z sequence for input sequence X = 1111110000. The flip-flops were cleared initially. f) An estimate of the maximum clock frequency for reliable operation. The setup time and D to Q propagation time are 6 and 55 ns, respectively. The multiplexer delays are 36 ns and 47 ns for Data and Select inputs, respectively. Assume a 10 ns delay for the inverter.…The state diagram of a Moore machine is shown below. This machine has one input (a), if we design its circuit by using two D-Flip Flops, which option will be the flip flops input equations? 9,9, = 00 01 1 10 Select one: O a. D1= Q1Q0' + Q1a, DO= Q1a' + Q1'a O b. D1=Q1'Q0 + Q1a' , D0=Q0a' + Q0'a O c. D1=Q1Q0' + Q1'a , D0=Q1' + Q0a' O d. None O e. D1= Q1'Q0 + Q1a' , D0= Q1a' + Q1'a
- Electrical Engineering Task Figure shows a BCD counter that produces a four-bit output representing the BCD code for number of pulses that have been applied to the counter input. In particular, the DCBA outputs will never represent a number greater than 1001,-91, (MOD-10). (MSB) Logic BCD counter circuit HIGH only when DCBA=210-310, or 910 a. Draw the logic circuit using the minimum expression and then explain its operation. B6. For the follow logic circuit system, the output f is: 5 (A) ab. (B) a + b. (C) a'+b'. (D) a'b'. a bDesign the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).
- For the input waveforms in Figure , what logic circuit will generate the output waveform shown? Explain in detail for each. Inputs B Output X Inputs B Output XAn asynchronous state machine has two inputs (X1 and X2) and one output (Z). The output is the same of the previous value if (X2=0) and (Z) equals to the value of (X1) if (X2=1). The designer needs for . . SR-flip ..... .... flops to construct the state machine. * O 2Design a combinational circuit using multiplexer for a car chime based on thefollowing system: A car chime or bell will sound if the output of the logic circuit(X) is set to a logic ‘1’. The chime is to be sounded for either of the followingconditions:• if the headlights are left on when the engine is turned off and• if the engine is off and the key is in the ignition when the door is opened.Use the following input names and nomenclature in the design process:• ‘E’ – Engine. ‘1’ if the engine is ON and ‘0’ if the engine is OFF• ‘L’ – Lights. ‘1’ if the lights are ON and ‘0’ if the lights are OFF• ‘K’ – Key. ‘1’ if the key is in the ignition and ‘0’ if the key is not in the ignition• ‘D’ – Door. ‘1’ the door is open and ‘0’ if the door is closed• ‘X’ – Output to Chime. ‘1’ is chime is ON and ‘0’ if chime is OFF