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- Suppose cache has a hit rate of 0.89 and access time of 5ns, main memory has a hit rate of 0.98 and access time of 60ns, and virtual memory has an access time of 700 us (microseconds). What is the average memory access time in us?Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?Suppose we have a processor with a base CPI of 2.0 assuming all references hit in the pnmary cache and a clock rate of 1000 MHz. The main memory access time is 100 ns. Suppose the miss rate per instruction is 5%. What is the revised CPI? How much taster will the machine run it we put a secondary cache (with 20-ns access time) that reduces the miss rate to memory to 2%
- Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
- A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes. a. What is the number of sets in the cache? b. What is the size (in bits) of the tag field per cache block? c. What is the number and size of comparators required for tag matching? d. How many address bits are required to find the byte offset within a cache block? e. What is the total amount of extra memory (in bytes) required for the tag bits?Assume a cache system has been designed such that cach block contains 4 words and the cache has 1024 lines, the cache can store up 10 1024 blocks. What line of the cache is supposed 10 hold the block that contains the word from the twenty-bit address JA456:? In addition, what is the tag number that will be stored with the block?True/False In a microprocessor of 32 bit addresses, the tag length will change if we design a two-way set-associate cache versus a four-way set-associative cache, with the same number of cache lines in each organization, and the same number of data bytes per set.
- A CPU has a 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set-associative cache with a cache line size of 16 bytes. Enter numeric values only. 1. What is the number of sets in the cache? 2. What is the size (in bits) of the tag field per cache line? 3. What is the number of comparators required for tag matching? bits 4. How many address bits are required to find the byte offset within a cache line? 5. What is the total amount of extra memory (in bytes) required for the tag bits? bytesFor a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0A virtual address of 32 bits is passed on to the TLB. If the number of entries (number of cache lines) in the TLB are 32, what is the width of the Tag field in the TLB?