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b) Let us assume that we have a write buffer (W.B.) and a small victim cache (V.C.) as shown in the figure. [3 points] Write buffer (W.B.). When there is a write to memory; this is sent to both L1 D- cache and W.B. at the same time. If there is a cache hit in L1 the W.B. discards the written word; otherwise, the written word is kept in the WB. WB access time is 1 cycle. Victim Cache (V.C.). The victim cache holds recently discarded blocks from L1 D- cache. When there is a data read sent to memory and there is an L1 D-cache miss the VC is accessed to check if the block is in this small VC. 56% of the time the block is found in the VC which has an access time of 1 cycle. Please notice that on a data read L1 D-cache miss, the request is sent to both VC and L2 at the same time. In this program, 13.6% and 19.2% are store and load instructions, respectively. Determine the new AMAT. Processor L1 D-cache V.C. L2-cache L3-cache Main W.B. In a split L1 cache organization the I-cache size is 16-KB and the D-cache is 32-KB; the access time for both caches is 1 cycle. The miss rates are given in the table below. There is a 256KB second level cache (L2) that is a unified cache and has a miss rate given in the table. Please assume that miss penalty is 20 cycles to get data from L2 cache. There is a 4MB third level cache (L3) that has a latency of 42 cycles; its miss rate is 1.28%. 124 cycles are required to get data from main memory. A program executes 8.6×10° instructions; 32.8% of the executed instructions are data references (i.e. loads or stores). AMAT = Hit Time + Miss Rate x Miss Penalty Cache miss rates a) Please determine the AMAT for this memory system. [7 points] Cache Size L1 I-Cache L1 D-Cache L2 Unified Cache 8 KB 0.82% 12.21% 8.63% 16 KB 0.38% 11.36% 6.75% L1: I D 32 KB 0.14% 10.67% 5.18% 64 KB 0.06% 10.15% 4.89% L2: U_cache 128 KB 0.03% 9.81% 3.66% 256 KB 0.002% 9.06% 2.76% L3: U_cache M: Main

b) Let us assume that we have a write buffer (W.B.) and a small victim cache (V.C.) as shown in the figure. [3 points] Write buffer (W.B.). When there is a write to memory; this is sent to both L1 D- cache and W.B. at the same time. If there is a cache hit in L1 the W.B. discards the written word; otherwise, the written word is kept in the WB. WB access time is 1 cycle. Victim Cache (V.C.). The victim cache holds recently discarded blocks from L1 D- cache. When there is a data read sent to memory and there is an L1 D-cache miss the VC is accessed to check if the block is in this small VC. 56% of the time the block is found in the VC which has an access time of 1 cycle. Please notice that on a data read L1 D-cache miss, the request is sent to both VC and L2 at the same time. In this program, 13.6% and 19.2% are store and load instructions, respectively. Determine the new AMAT. Processor L1 D-cache V.C. L2-cache L3-cache Main W.B. In a split L1 cache organization the I-cache size is 16-KB and the D-cache is 32-KB; the access time for both caches is 1 cycle. The miss rates are given in the table below. There is a 256KB second level cache (L2) that is a unified cache and has a miss rate given in the table. Please assume that miss penalty is 20 cycles to get data from L2 cache. There is a 4MB third level cache (L3) that has a latency of 42 cycles; its miss rate is 1.28%. 124 cycles are required to get data from main memory. A program executes 8.6×10° instructions; 32.8% of the executed instructions are data references (i.e. loads or stores). AMAT = Hit Time + Miss Rate x Miss Penalty Cache miss rates a) Please determine the AMAT for this memory system. [7 points] Cache Size L1 I-Cache L1 D-Cache L2 Unified Cache 8 KB 0.82% 12.21% 8.63% 16 KB 0.38% 11.36% 6.75% L1: I D 32 KB 0.14% 10.67% 5.18% 64 KB 0.06% 10.15% 4.89% L2: U_cache 128 KB 0.03% 9.81% 3.66% 256 KB 0.002% 9.06% 2.76% L3: U_cache M: Main

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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b) Let us assume that we have a write buffer (W.B.) and a small victim cache (V.C.) as shown in the figure. [3 points] Write buffer (W.B.). When there is a write to memory; this is sent to both L1 D- cache and W.B. at the same time. If there is a cache hit in L1 the W.B. discards the written word; otherwise, the written word is kept in the WB. WB access time is 1 cycle. Victim Cache (V.C.). The victim cache holds recently discarded blocks from L1 D- cache. When there is a data read sent to memory and there is an L1 D-cache miss the VC is accessed to check if the block is in this small VC. 56% of the time the block is found in the VC which has an access time of 1 cycle. Please notice that on a data read L1 D-cache miss, the request is sent to both VC and L2 at the same time. In this program, 13.6% and 19.2% are store and load instructions, respectively. Determine the new AMAT. Processor L1 D-cache V.C. L2-cache L3-cache Main W.B.
Transcribed Image Text:b) Let us assume that we have a write buffer (W.B.) and a small victim cache (V.C.) as shown in the figure. [3 points] Write buffer (W.B.). When there is a write to memory; this is sent to both L1 D- cache and W.B. at the same time. If there is a cache hit in L1 the W.B. discards the written word; otherwise, the written word is kept in the WB. WB access time is 1 cycle. Victim Cache (V.C.). The victim cache holds recently discarded blocks from L1 D- cache. When there is a data read sent to memory and there is an L1 D-cache miss the VC is accessed to check if the block is in this small VC. 56% of the time the block is found in the VC which has an access time of 1 cycle. Please notice that on a data read L1 D-cache miss, the request is sent to both VC and L2 at the same time. In this program, 13.6% and 19.2% are store and load instructions, respectively. Determine the new AMAT. Processor L1 D-cache V.C. L2-cache L3-cache Main W.B.
In a split L1 cache organization the I-cache size is 16-KB and the D-cache is 32-KB; the access time for both caches is 1 cycle. The miss rates are given in the table below. There is a 256KB second level cache (L2) that is a unified cache and has a miss rate given in the table. Please assume that miss penalty is 20 cycles to get data from L2 cache. There is a 4MB third level cache (L3) that has a latency of 42 cycles; its miss rate is 1.28%. 124 cycles are required to get data from main memory. A program executes 8.6×10° instructions; 32.8% of the executed instructions are data references (i.e. loads or stores). AMAT = Hit Time + Miss Rate x Miss Penalty Cache miss rates a) Please determine the AMAT for this memory system. [7 points] Cache Size L1 I-Cache L1 D-Cache L2 Unified Cache 8 KB 0.82% 12.21% 8.63% 16 KB 0.38% 11.36% 6.75% L1: I D 32 KB 0.14% 10.67% 5.18% 64 KB 0.06% 10.15% 4.89% L2: U_cache 128 KB 0.03% 9.81% 3.66% 256 KB 0.002% 9.06% 2.76% L3: U_cache M: Main
Transcribed Image Text:In a split L1 cache organization the I-cache size is 16-KB and the D-cache is 32-KB; the access time for both caches is 1 cycle. The miss rates are given in the table below. There is a 256KB second level cache (L2) that is a unified cache and has a miss rate given in the table. Please assume that miss penalty is 20 cycles to get data from L2 cache. There is a 4MB third level cache (L3) that has a latency of 42 cycles; its miss rate is 1.28%. 124 cycles are required to get data from main memory. A program executes 8.6×10° instructions; 32.8% of the executed instructions are data references (i.e. loads or stores). AMAT = Hit Time + Miss Rate x Miss Penalty Cache miss rates a) Please determine the AMAT for this memory system. [7 points] Cache Size L1 I-Cache L1 D-Cache L2 Unified Cache 8 KB 0.82% 12.21% 8.63% 16 KB 0.38% 11.36% 6.75% L1: I D 32 KB 0.14% 10.67% 5.18% 64 KB 0.06% 10.15% 4.89% L2: U_cache 128 KB 0.03% 9.81% 3.66% 256 KB 0.002% 9.06% 2.76% L3: U_cache M: Main
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