For the following State table: 1. Draw its equivalent state diagram 2. Write a VHDL code that implements the FSM described by this state table Next state Present Output state ab=00 01 10 11 S Go Go G₁ G₁ Ho 0 G₁ Go G₁ G₁ Ho 1 Ho Gì Ho Ho Hi 0 H₁ Gì Ho Ho Hi 1

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