Question 9 (14 ListenGiven the following VHDL Definition:entity MyDesign isportA: in std logic vector(7 downto 0);B: in std_logic_ vector(3 downto 0);X: out std _logic;Y: out std logic_vector(3 downto 0)end MyDesign;architecture MyDesign_arch of MyDesign isbeginX <= (A(6) or B(2)) and B(3):Y <= B(2) & A(5 downto 2) & "101";end MyDesign archIf A is "10110001" and B is "0110", What is the resultant value of Y?(Don't forget to write the answer in the proper format for vector and/or signalvalues)

Answered: Image /qna-images/answer/caaf27cd-5dee-4926-9cbe-e7e09df43c13.jpg

Answered: entity MyDesign is port A: in std logic…

entity MyDesign is port A: in std logic vector(7 downto 0); B: in std logic_vector(3 downto 0): X: out std _logic3; Y: out std logic_vector(3 downto 0) end MyDesign;

C++ for Engineers and Scientists

4th Edition

ISBN:9781133187844

Author:Bronson, Gary J.

Publisher:Bronson, Gary J.

Chapter12: Adding Functionality To Your Classes

Section12.5: Virtual Functions

Problem 3E

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