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A typical computer system has a MM of size 4Gwords, and a 4-way cache memory of 256Kwords. The cache line size is 128words, while the cache miss penalty is 100 clock cycles. a) How many sets are in that cache? what is the tag size? b) Suppose the same cache described in part a is used, the CPU generates the following MM address to read an instruction from the MM in case of a cache miss. Address generated by CPU: n=#003EF6FH What would be the word number the CPU is requested? In which MM block this word should belongs to? Also, in which cache set this word and the whole MM block must be stored? e) If the cache hit time is 1 clock cycle, what is the hit rate would be required to achieve an AMAT equal to 3.86 clock cycle?

A typical computer system has a MM of size 4Gwords, and a 4-way cache memory of 256Kwords. The cache line size is 128words, while the cache miss penalty is 100 clock cycles. a) How many sets are in that cache? what is the tag size? b) Suppose the same cache described in part a is used, the CPU generates the following MM address to read an instruction from the MM in case of a cache miss. Address generated by CPU: n=#003EF6FH What would be the word number the CPU is requested? In which MM block this word should belongs to? Also, in which cache set this word and the whole MM block must be stored? e) If the cache hit time is 1 clock cycle, what is the hit rate would be required to achieve an AMAT equal to 3.86 clock cycle?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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A typical computer system has a MM of size 4Gwords, and a 4-way cache memory of 256Kwords. The cache line size is 128words, while the cache miss penalty is 100 clock cycles. a) How many sets are in that cache? what is the tag size? b) Suppose the same cache described in part a is used, the CPU generates the following MM address to read an instruction from the MM in case of a cache miss. Address generated by CPU: n = #003EF6FH n= What would be the word number the CPU is requested? In which MM block this word should belongs to? Also, in which cache set this word and the whole MM block must be stored? e) If the cache hit time is 1 clock cycle, what is the hit rate would be required to achieve an AMAT equal to 3.86 clock cycle?
Transcribed Image Text:A typical computer system has a MM of size 4Gwords, and a 4-way cache memory of 256Kwords. The cache line size is 128words, while the cache miss penalty is 100 clock cycles. a) How many sets are in that cache? what is the tag size? b) Suppose the same cache described in part a is used, the CPU generates the following MM address to read an instruction from the MM in case of a cache miss. Address generated by CPU: n = #003EF6FH n= What would be the word number the CPU is requested? In which MM block this word should belongs to? Also, in which cache set this word and the whole MM block must be stored? e) If the cache hit time is 1 clock cycle, what is the hit rate would be required to achieve an AMAT equal to 3.86 clock cycle?
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