A computer system uses a simple base/bounds register pair to virtualize address spaces. In each of the traces below, your job is to fill in the missing values of virtual addresses, physical addresses, ba and/or bounds registers. In some cases, it is not possible to provide an exact value. If so, please specify a range (e.g. greater than 100), or value that is not a single number. Scenario 1: Virtual Address 100 300 699 700 Scenario 2: Virtual Address 300 1600 1801 2801 Physical Address 600 800 1199 fault Physical Address 1500 2800 ? 4001 Base? 500 Bounds? 699 Base? Bounds?

A computer system uses a simple base/bounds register pair to virtualize address spaces. In each of the traces below, your job is to fill in the missing values of virtual addresses, physical addresses, ba and/or bounds registers. In some cases, it is not possible to provide an exact value. If so, please specify a range (e.g. greater than 100), or value that is not a single number. Scenario 1: Virtual Address 100 300 699 700 Scenario 2: Virtual Address 300 1600 1801 2801 Physical Address 600 800 1199 fault Physical Address 1500 2800 ? 4001 Base? 500 Bounds? 699 Base? Bounds?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 22VE

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Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?
Memory address Data According to the memory view given below, if RO = Ox20008002 then LDRSB r1, [r0, #-4] is executed as a result of r1 = ?(data overlay big endian)? Øx20008002 ØXA1 Øx20008001 ØXB2 Øx20008000 Øx73 ØX20007FFE ØXD4 ØX20007FFE Lütfen birini seçin: O A. R1 = 0X7F O B. R1 = Oxffffffd4 O C. R1 = Oxffffff7F O D. R1=0XD4000000 O E. R1 = 0XD4
In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.
Suppose a computer using direct mapped cache has 232232 words of main memory and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? To which cache block will the memory reference 000063FA16 map?
3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16- byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown below: Tag 4 bits Block 2 bits Offset 2 bits The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables: a) Address Hit Reference or Miss Comments b) Show the final contents of cache for direct addressing: Block Cache Contents Tag (represented by address)
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. 8 bits are used for offset, 8 bits are used for page # and the max number of pages a process can have is 256. e. Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert hexadecimal numbers to decimal ones.) 0x0389 0xDF78 0x0245 0x8012 f) Now, suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) g)What is the size of the two-level page table…
A cache is set up with a block size of 32 words. There are 64 blocks in cache and set up to be 4-way set associative. You have byte address 0x8923. Show the word address, block address, tag, and index Show each access being filled in with a note of hit or miss. You are given word address and the access are: 0xff, 0x08, 0x22, 0x00, 0x39, 0xF3, 0x07, 0xc0.
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Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
2. A memory location has a logical address where the segment address is the first four digits is your roll number and the offset address is the last four digits of your roll number. Find the physical address of the memory location. [example: if your roll number is 1234200516789, then the segment address is 1234h and the offset address is 6789h]
An address space in the memory map starts at address Ox40000000 and ends at address O×40000FFE. What is the size of the space if the data size is 2 bytes? 16k bytes 4k bytes 2k bytes 8k bytes