12. This problem is about designing a logie module with three inputs z, y, z and produces seven outputs a, b, c, d, e, f. 9 (that feed into a 7-segment display as shown in Figure 2.63 of the text, page 97). The three inputs bits rys are used to identify letters 'L', '0', 'G', 'T, 'C' as shown in the table below (unused inputs (101 to 111) correspond to don't care outputs. y Output letter 000 001 010 L NOO 0 011 100 The figure below shows the depiction of the output letters in the 7-segment display. 88888 I (a) Draw a truth table for the circuit, using the three inputs x,y,z to enumerate the values of the outputs a,b,c,d,e,f.g. Show the don't care values in your truth table. (b) Use Karnaugh maps to determine the logic for each output. Keep in mind that your objective is to reduce the cost of the final (AND/OR/NOT) circuit. You can use POS and/or SOP implementations for the outputs. Keep in mind that some of the outputs may share implicants that would correspond to sharing portions of the circuit. (e) Draw your circuit and determine its cost. In determining the cast of a circuit, you may assume that ... y.,2' are all available (at no cost).

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12. This problem is about designing a logic module with three inputs z, y, 2 and produces
seven outputs a, b, c, d, e, f, g (that feed into a 7-segment display as shown in Figure 2.63
of the text, page 97). The three inputs bits ryz are used to identify letters 'L', '0', 'G',
'T', 'C' as shown in the table below (unused inputs (101 to 111) correspond to don't
care outputs.
y Output letter
000
001
010
L
0
011
100
The figure below shows the depiction of the output letters in the 7-segment display.
I
88888
(a) Draw a truth table for the circuit, using the three inputs x,y,z to enumerate the
values of the outputs a, b, c, d, e, f, g. Show the don't care values in your truth
table.
(b) Use Karnaugh maps to determine the logic for each output. Keep in mind that
your objective is to reduce the cost of the final (AND/OR/NOT) circuit. You can
use POS and/or SOP implementations for the outputs. Keep in mind that some
of the outputs may share implicants that would correspond to sharing portions of
the circuit.
(e) Draw your circuit and determine its cost. In determining the cost of a circuit,
you may assume that a, a,, y, a, a' are all available (at no cost).
Transcribed Image Text:12. This problem is about designing a logic module with three inputs z, y, 2 and produces seven outputs a, b, c, d, e, f, g (that feed into a 7-segment display as shown in Figure 2.63 of the text, page 97). The three inputs bits ryz are used to identify letters 'L', '0', 'G', 'T', 'C' as shown in the table below (unused inputs (101 to 111) correspond to don't care outputs. y Output letter 000 001 010 L 0 011 100 The figure below shows the depiction of the output letters in the 7-segment display. I 88888 (a) Draw a truth table for the circuit, using the three inputs x,y,z to enumerate the values of the outputs a, b, c, d, e, f, g. Show the don't care values in your truth table. (b) Use Karnaugh maps to determine the logic for each output. Keep in mind that your objective is to reduce the cost of the final (AND/OR/NOT) circuit. You can use POS and/or SOP implementations for the outputs. Keep in mind that some of the outputs may share implicants that would correspond to sharing portions of the circuit. (e) Draw your circuit and determine its cost. In determining the cost of a circuit, you may assume that a, a,, y, a, a' are all available (at no cost).
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