1. Given the following memory locations, identify the "index" in the Cache table where the location will be stored, and the "Tag", under the following specifications: Cache size = 2¹ memory blocks, each block contains 8 words, each word contains 4 bytes. Locations: 1F2A 387B D482 5C19 Identify the locations using a) Direct Mapped Cache, b) Fully Associative Cache, and c) 4-way Set Associative Cache Hint: First convert the address to bits. Find the block address by remembering that each word is 4 bytes and each block has 8 words. After you identify the "bits" for the index and tag, convert the bits back to hexa-decimal notation.

1. Given the following memory locations, identify the "index" in the Cache table where the location will be stored, and the "Tag", under the following specifications: Cache size = 2¹ memory blocks, each block contains 8 words, each word contains 4 bytes. Locations: 1F2A 387B D482 5C19 Identify the locations using a) Direct Mapped Cache, b) Fully Associative Cache, and c) 4-way Set Associative Cache Hint: First convert the address to bits. Find the block address by remembering that each word is 4 bytes and each block has 8 words. After you identify the "bits" for the index and tag, convert the bits back to hexa-decimal notation.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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For a direct-mapped cache with 64KİB data, 8-word blocks, and 32-bit addresses, answer the following questions: a) What is the number of blocks/lines in the cache? b) Identify the bits in the 32-bit address that are used as index bits? c) Identify the bits in the 32-bit address that are used as tag bits? d) What is the total number of bits in this cache (including tag field and valid field)? e) Identify the block number in the cache to which the following 32-bit memory address maps: Ox00003Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
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D Question 24 Assume the address format for a 2-way set-associative cache is as follows: 4 bits 2 bits 2 bits Tag Set Offset 8 bits Given the cache directory is as shown in the diagram below, indicate which cache set the memory reference Ox5E maps to (express set number in decimal) and whether it results in a cache hits or miss Copyright © 2016-2021 by A.Berrached-All Rights Reserved. Set Tag valid 00 1 10 01 1 1 10 11 Question 25 0000 1101 0000 0001 0000 1011 0101 1000 1 1 0
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2-Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. a. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. 42, 180, 46, 185, 189, 3, 181, 43, 6, 189, 65, 190 b. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with four-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. c. For each of these references, identify the binary address, the tag, and the index given a two way associative cache with two-word blocks and a total size of 4 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty d. For each of these…