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San Francisco State University *

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CSE203

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Electrical Engineering

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Jan 9, 2024

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pdf

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4

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Practice Questions: Q1) Consider the following RISC-V assembly code: 1) ld x1,45(x2) 2) add x7,x1,x5 3) sub x8,x1,x6 4) or x9,x5,x1 5) bne x11, x7, target 6) add x10,x8,x7 7) xor x2,x3,x4 Identify each dependence; list the two instructions involved; identify which instruction is dependent; and, if there is one, name the storage location (register or memory). Solution: Inst (2) is dependent on inst (1) through x1 Inst (3) is dependent on inst (1) through x1 Inst (4) is dependent on inst (1) through x1 Inst (5) is dependent on inst (2) through x7 Inst (6) is dependent on inst (2) through x7 Inst (6) is dependent on inst (3) through x8 Q2) Indicate the data dependences in the following RISC-V code sequence: 1) add x1, x2, x3 2) lw x4, 0(x1) 3) addi x5, x1, 100 4) sw x4, 0(x5) 5) or x4,x3,x5 Solution: Inst (2) is dependent on inst (1) through x1 Inst (3) is dependent on inst (1) through x1 Inst (4) is dependent on inst (2) through x4 Inst (4) is dependent on inst (3) through x5 Inst (5) is dependent on inst (3) through x5 Q3) Please identify all data dependencies beside each instruction:
1) lw x2, 60(x1) 2) lw x1, 40(x2) 3) slt x1, x1, x2 4) sw x1, 20(x2) Solution: lw x2, 60(x1) No dependencies lw x1, 40(x2) WAR on x1 from instr 1 RAW on x2 from instr 1 slt x1, x1, x2 WAR on x1 from instr 1 RAW on x2 from instr 1 WAW on x1 from instr 2 RAW on x1 from instr 2 sw x1, 20(x2) RAW on x2 from instr 1 WAR on x1 from instr 1 RAW on x1 from instr 3 Q4) Latencies of the major functional components of the single-cycle datapath are: Memory read: 4 ns Memory write: 4 ns Register file read: 2 ns Register file write: 2 ns ALU: 3 ns The latencies of all other components of the datapath is negligible. a) Compute the maximum possible clock frequency of the single-cycle processor.
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