HW 1 (2)

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Electrical Engineering

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Apr 3, 2024

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EE 5324 Spring 2024 HW #1 Due 02/13/24 (Tuesday), Submitted to Canvas, Softcopy 1. Please select True or False for the following statements. No explanation is needed. (True / False) Sheet resistance of metal interconnect increases from M1 to M8. (True / False) Layout guidelines follow the DRC rules to improve the manufacturing yield. (True / False) The timing analysis performed to characterize each standard cell is static. (True / False) Compared to latch-based designs, flip-flop based designs are easier to verify. 2. To maximize performance while minimizing leakage power, which is the design choice? a. High-V th devices for critical paths and high-V th devices for non-critical paths b. Low-V th devices for critical paths and high-V th devices for non-critical paths c. High-V th devices for critical paths and low-V th devices for non-critical paths d. Low-V th devices for critical paths and low-V th devices for non-critical paths 3. A latch design has the setup time t setup = 50ps, the hold time t hold = 100ps, t D2Q = 150ps and t C2Q = 100ps. We use a pair of these latches to construct a flip-flop, with perfect clock signals Φ and Φ � (i.e., no skew or jitter), as shown in the figure below. If we want this FF has t C2Q = 100ps, what is the setup time of the FF? What is the hold time of the FF? 4. In this problem, all sequential elements are identical flip-flops. Assume the following parameters of the FFs: t C2Q = 150ps, t setup = 50ps, and t hold = 100ps. The clock has no jitter. Please clearly show how you solve each problem. If there are only answers, no points will be given. a. The pipeline structure is shown below, with three logic modules. The maximum delay ( t LM ) and the minimum delay ( t LS ) of each module are annotated. What is the minimum clock period ( T ) if there is no clock skew? D Q Φ Φ � t setup = ; t hold = ;

b. Assume there exist clock skews: t skew1-2 = -100ps (i.e., Φ 1 is behind Φ 2 by 100ps) and t skew1-3 = 50ps (i.e., Φ 3 is behind Φ 1 by 50ps). What is the minimum clock period now? Please highlight the logic module that defines the minimum clock period. c. Assume t skew1-3 is fixed at 50ps. How negative can t skew1-2 be before this pipeline design fails a hold time constraint? Please highlight the logic module that has the hold time violation. d. If you are able to set the values of t skew1-2 and t skew1-3 , what are the values would you choose in order to minimize the clock period of this pipeline design? What would be the minimum clock period in this case? [ Hint : Given a skew, the minimum T may increase for a logic module; meanwhile, it may decrease for another logic module due to the loop structure.] T = T = t skew1-2 = T =

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